Performace Evaluation of LMS and DLMS Digital Adaptive FIR Filters by Realization on FPGA

Abstract

The aim of this paper is to impalement the adaptive digital Least Mean Square (LMS) and delayed-LMS (DLMS) Finite Impulse Response (FIR) filters on Field Programmable Gate Array (FPGA) chips for typical noise cancellation applications and compare the behavior of LMS and DLMS adaptive algorithms in terms of chip area utilization and the filter critical path time or filter frequency. The direct FIR architecture is considered for filter designing and the VHDL hardware description language is used for algorithm modeling. The obtained results by the synthesize tool QUARTUS II on a single STRATIX II chip, EP2S15F484C3, from ALTERA Inc. demonstrate that the DLMS algorithm which has a pipeline architecture is faster than LMS algorithm while it uses more chip area due to using extra registers.