A Fast Radix-4 Algorithm and Architecture for DHT

Abstract

The radix-4 decimation-in-time fast Hartley transform and algorithm for DHT was introduced by Bracewell. A set of fast algorithms were further developed by Sorenson et al. In this paper, a fast radix-4 decimation-in-time algorithm that requires less number of multiplications and additions is proposed. It utilizes four different structures in the signal flow diagram. It exhibits a recursive pattern and is modular. The operational counts for the proposed algorithm are determined and verified by implementing the program in C. An analog architecture to implement the algorithm is proposed. The validity of the same is tested by simulating it with the help of the Orcad PSpice.