VLSI Technology Used in Autoscan Design for Bench Mark Circuits

Abstract

Autoscan, a design for testability (DFT) technique for synchronous sequential circuits. Scan operation under autoscan improves circuit testability by allowing the shift operations. A scan select line is used for controlling the shift operations. Autoscan uses scan chains similar to conventional scan. i.e. All or most of the flip-flop of a circuit are included in scan chains.

                Full scan is a widely accepted method for synchronous sequential circuit. However, the test application time required by full scan could be high because of   the necessity to scan in and scan out test vectors. In this work, without external scan inputs or outputs are presented that aims to achieve maximum fault coverage’s and to reduce the test application time in circuits.   

In conventional scan design, all the flip-flop are in unidirectional. But in this mode, these restrictions are eliminated. Instead, it is possible to define any number of scan chains with different direction and different sources. Autoscan allows us to detect almost all the faults that are detectable using normal conventional scan design. Autoscan uses random test sequences, because random test patterns covers more fault coverage’s than sequential test patterns.

Linear feedback shift register (LFSR) is widely used for generating the Random test patterns. The random test sequences are independent of the particular autoscan configuration. They applied to the circuits from an external source. Experimental results for various Bench mark Circuits are given to show the effectiveness of this method.