Leakage Power Reduction in CMOS

Abstract

The advantage of scaling devices is to achieve high performance, low power, large integration and low cost continues to be attractive to the semiconductor industries. However, increasing variability in the device characteristics, soft errors and device degradation in CMOS technologies pose major challenges in the future scaling. Variation in process, voltage and temperature cause uncertainty in the worst case critical path delays. Delay Margins or Voltage Margins are added to obtain fully functional chips, but results in high power consumption and/or performance loss.

In electronics, a flip-flop or latch is a circuit that has two stable states and can be used to store state information. The circuit can be made to change state by signals applied to one or more control inputs and will have one or two outputs. It is the basic storage element in sequential logic. Flip-flops and latches are a fundamental building block of digital electronics systems used in computers, communications, and many other types of systems. In VLSI systems, the clock system consumes anywhere between 20-50% of the total chip power with approximately 90% of the clocking power used to drive storage elements such as flip-flops. The significant power consumption of the clock system is mainly due to the 100% transition probability of the clock signal.